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IEEE Chapter talk - Opportunities and Challenges for Three-Dimensional (3-D) Integrated Circuits - Mr. Vasilis Pavlidis

  • Στοιχεία επικοινωνίαςΘάνος Στουραΐτηςemail:thanos AT ece.upatras.gr

12.11.2007, Αίθουσα ΗΛ1 Τμήματος Ηλεκτρολόγων Μηχανικών και Τεχνολογίας Υπολογιστών

Invitation to attend a lecture on "Opportunities and Challenges for Three-Dimensional (3-D) Integrated Circuits", on 13:00 - 14:00, Monday, November 12, 2007, at ΗΛ1 room (Electrical and Computer Engineering Department, University of Patras campus), University of Patras, by Vasilis Pavlidis, University of Rochester, NY

The lecture is sponsored by the Greek chapters of the Signal Processing and Circuits and Systems societies of the Institute of Electrical and Electronic Engineers (IEEE)

Abstract

Three-dimensional (3-D) or vertical integration is a promising design paradigm to overcome the existing interconnect bottleneck in integrated systems. The opportunities offered by this novel technology are discussed in this talk. In addition, the manufacturing and design challenges for 3-D ICs are reviewed. Specific interconnect and physical design techniques for vertically integrated systems are also presented. Finally, some of the open research problems related to this innovative technology are briefly discussed.

Biography

Vasilis F. Pavlidis received the B.S. and M.Eng. in electrical and computer engineering from the Democritus University of Thrace, Xanthi, Greece, in 2000 and 2002, respectively. He is working toward the Ph.D. degree in the Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY. From 2000 to 2002, he was with INTRACOM S.A., Athens, Greece. During summer 2007, he was with Synopsys Inc. as a summer intern. His current research interests are in the area of interconnect modeling, 3-D integration, networks-on-chip, and related design issues in VLSI.

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